The main goals of physical design are 

1. Optimizing Power, 

2. Performance, and 

3. Area. 

Place and route play a crucial role in this process, as it involves placing all the cells and memories present in the design and routing them according to the target technology. This step determines the chip’s core area, core frequency, and core power.

The ultimate objective is to ensure that the output chip has a minimal area, meets timing requirements, and consumes low Power. In the initial stage of the physical design flow, the required files for the related blocks are imported into the tool after partitioning the chip into blocks.

Inputs for Place and Route

Important inputs required for place and route are:

1. Netlist (.vg file): This file contains the logical connectivity of all cells in the design, and it comes from the synthesis team.

2. Synopsys Design Constraints (.SDC file): This file consists of timing constraints that require the design to meet timing requirements.

3. Timing Libraries (.lib file): These libraries contain timing and functionality information of standard cells, macros, PVT corners, area of cells, leakage power information of cells, and slew rate of cells.

4. Physical Libraries (.lef files): These libraries provide physical information of all standard cells and macros. They contain details such as pin locations, pin layers, pin directions, height and width of pins and cells, and technology information.

5. Technology File (.tf): The technology file provides information about the desired technology for implementing the design physically. 

It specifies details of the metal layer technology parameters, such as 

          –Name and number of each metal layer, 

          –Physical and electrical characteristics of each metal layer and 

          –Design rules like minimum width and minimum spacing.

6. ITF (Interconnect Technology File): This file is used to extract the chip’s RC values.

7. TLUPlus Files: These files, also known as Table Lookup Files, serve the following main functions:

          –Provide the R and C parasitics of metal per unit length to calculate net delays.

          –Extract the parasitics from the ITF file if you don’t have TLUPlus files.

          –To load TLUPlus files, you need:

                    Min tlu+ file

                    Max tlu+ file

                    Map file

These input files are crucial for the place and route process, as they provide the necessary information for the tools to perform physical design tasks such as placement, routing, and timing optimization.

Sanity Checks

Sanity checks are crucial in the Place and Route stage to ensure the correctness and quality of the inputs received from the library and synthesis teams. This way, potential problems are identified and addressed early in the design flow, preventing later-stage issues that could be more time-consuming and costly to fix.

Sanity checks can be broadly categorized into three main types:

1. Design Checks: 

These checks verify the quality of the netlist and report any issues, such as 

Floating pins

Multidrive nets

Undriven input ports

Unloaded outputs

Unconstrained pins

Instances and references have mismatched pins

Tristate buses with non-tristate drivers

2. SDC Checks: 

SDC (Synopsys Design Constraints) checks ensure that timing constraints are properly defined and applied. 

Identify unconstrained paths

Verify that the clock is reaching all clock pins of the flip-flops

Check for multiple clocks driving the same registers

Report unconstrained endpoints

Identify missing input/output delay or slew/load constraints

3. Library Checks: 

Library checks validate the consistency between logical and physical libraries, ensuring they are high-quality and error-free. 

Identify missing cells

Identify missing metal or pins in the physical and logical libraries

Identify other library-related issues

These checks are necessary to avoid suboptimal results, timing violations, and potential functional failures in the final design.

Steps Involved in Place and Route

Considering the high complexity of Physical Design, it can be divided into several important steps as follows;

1.Floor Planning

2.Placement

3.Clock Tree Synthesis

4.Routing

1. Floor Planning

Floor planning is crucial in Physical Design, as the quality of the chip or design implementation heavily depends on the effectiveness of the floor plan.

A well-executed floor plan results in an ASIC design with higher performance and optimal area utilization.

During this stage, macros (such as memories and analog blocks) are strategically placed around the core to enhance area efficiency, timing, and power consumption.

Proper macro placement significantly impacts the quality and performance of the ASIC design and can be done manually or automatically.

Manual macro placement is more efficient when dealing with small macros, utilizing connectivity information between macros and IO pins/pads.

Automatic macro placement is preferred when there are many macros, ensuring efficient and optimal placement.

2. Placement

Placement is a crucial step in the physical design flow that involves positioning the standard cells on the chip layout. This stage aims to optimize design metrics like timing, congestion, and power consumption. 

Placement typically involves the following steps:

Pre-placement

Coarse placement

Legalization

High Fanout Net Synthesis (HFNS)

Iterations for congestion, timing, Design Rule Violations (DRV), and power optimization

Timing optimization iterations

Scan-chain reordering

Tie cell insertion.

3. Clock Tree Synthesis

CTS involves connecting clocks to all clock pins of sequential circuits using inverters and buffers to balance skew and minimize insertion delay.

Clock balancing ensures all clock pins are driven by a single clock source, which is crucial for meeting design constraints and achieving optimal performance.

4. Routing

The routing process involves creating physical connections between or among the signal pins according to the target technology’s design rules (DRC). The interconnect wires are laid out during routing to establish the required connections between the placed cells and macros, ensuring that all nets are routed without any open connections or shorts.

EDA Tools for Place and Route

The two most popular EDA tools used for place and route are Innovus from Cadence and ICC from Synopsys.

1. Innovus from Cadence

Innovus is a powerful physical implementation system that provides a comprehensive solution for advanced-node designs. Its robust and flexible implementation flow enables designers to achieve performance, power, and area targets.

Innovus supports various design styles, including standard cells, mixed-signal, and analog/RF designs.

1. ICC from Synopsys

ICC (Integrated Circuit Compiler) is Synopsys’ physical implementation solution for digital and mixed-signal designs. It provides a comprehensive set of tools and features for place and route, timing optimization, and signal integrity analysis.

The choice between the two tools often depends on design complexity, technology node, design style, and organizational tool flows.

Conclusion

By optimizing these physical design stages, VLSI designers can create faster, more reliable, and more power-efficient circuits that drive the electronics industry. Careful consideration of physical design aspects can lead to significant improvements in circuit performance, reliability, and power consumption, enabling the development of cutting-edge electronic devices and systems.