Optimising Power Efficiency in SoC Designs A Guide to Low Power Verification

Optimising Power Efficiency in SoC Designs: A Guide to Low Power Verification

Power consumption is among the most essential design metrics in current Silicon-On-Chip (SoC) designs. Using low power verification, the users can significantly reduce the power consumption of design by defining the power-aware strategies using Unified Power Format with design at different levels: simulation level, netlist level, and P & R level.

What is Low Power Verification?

Low Power Verification provides a method for enabling the design to be power-aware. It uses power-reducing techniques or a Unified Power Format (UPF). Low power verification offers a way to reduce the power of design, whether it is dynamic, peak or static power.

UPF tools help to find inconsistencies in the power model defined using UPF and power-aware tool estimates and manage the tool power of the design.

Functional Verification vs Low Power Verification

Functional verification intrinsically assumes that there are no power-related design issues and only verifies the behaviour/functionality of the RTL. On the other hand, Low power verification uses the UPF to ensure the design’s behaviour is proper in the power environment.

Why Low Power Verification Matters?

The following equation defines the total power in the circuit

Dynamic and static power are the primary sources of power dissipation in CMOS-based design circuits. Dynamic power refers to the energy consumed by the circuit during its operation, driven by factors such as switching activity and operating frequency.

In contrast, static power represents the power consumed when the circuit is idle, influenced by leakage currents and other static factors. Effective dynamic and static power management is crucial for optimising overall power efficiency in semiconductor designs.

Operating Frequency
Voltage
Transition time
Capacitive Load of circuit
Leakage current and peak current

So, low power verification helps reduce dynamic power, static power (leakage power), and peak power.

Key Methods for Enhancing Power Efficiency
This section will provide some details about low-power techniques. These are

Clock Gating: This low-power technique optimises flops in a clock gating structure to reduce the switching power (dynamic power). This technique helps to reduce power and area. It is done by a logic synthesis tool to perform Clock Gating.

Multi VDD (Multi Voltage): Dynamic power consumption is directly influenced by the power supply voltage. In the context of low-power design techniques, multi-voltage design involves connecting different parts of the circuit to varying voltage levels, tailored to specific operational needs. This approach, known as multi-voltage design, optimises power efficiency by adjusting voltages dynamically across different sections.

Power Gating: Power Gating effectively shuts off the power supply for a block whenever it is not required, as per application, resulting in both static and dynamic power savings.

It is a very effective technique for reducing power consumption. In order to achieve Power Gating, power switches must be implemented in the design. These switches are nothing more than level shifters. The level shifter blocks the leakage current from the power-on to shut-off domains.

Isolation cell isolates the shut-off domain from the shut-on domain. The isolation cell ensures that the signals driven by the off-domain to the on-domain will not corrupt the on-domain. It always makes only the known values (0/1) propagate to the on domain when the driving domain is powered off.

Power Gating with Retention

As we discussed, power gating is a very aggressive technique for saving power. In this technique, the shut-off domain requires isolation and retention cells.

The retention cell helps store the last status of the shut-off domain. It helps to prevent any functional issues due to the power shut-off domain.

Once the domain is on, the retention cell retains the last state of the block.

Figure: Power Gathering Technique Implementation

The above Figure shows the power Gating implementation using Unified Power Format (UPF). Power intent is defined using the below cells.

Level Shifter Cell: It manages the voltage difference of domains.
Isolation Cell: It isolates the power off domains from the power on domains.
Retention Cell: It saves the data of the last states before shutting off and also restores it once it is turned on.

Challenges in Low Power Verification

Power Gating reduces the power significantly, but it also increases

The complexity of design.
Multi-VDD and Voltage scaling designs require signal resolution.
It demands separate power intent.
Tools should be available to sense that power-aware intent can analyze power.

Tools and Technology

Many tools are available for low-power verification and power-aware simulation. Here are the lists

UPF tools:

Cadence Low Power (CLP)

Synopsis VC LP (Verification compiler Low power)

Power Aware Simulation Tools

Siemens Questa Power Aware

Synopsys VCS power aware

Cadence Xcelium Power Aware

Conclusion

Static dissipation on the chip is increasing day by day due to a very high level of integration. Today, high-speed clocks are contributing significant dynamic dissipation. To reduce the overall static and dynamic power, the User should apply Multi VDD, Clock Gating, Power Gating, and Power Gating with Retention to take advantage of these techniques.

Explore More: Formal Verification: Ensuring Reliability and Quality in Complex Systems

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