Verifying AI Chips at RTL: How Foundation Models Are Transforming Design Assurance Modern AI chips are not general-purpose processors. Their RTL design logic is optimized not for instruction throughput, but for dataflow acceleration, parallel computation, and high-efficiency matrix operations. These chips integrate systolic arrays, sparsity-aware data paths, configurable tensor engines, and hierarchical memory systems. This […]

Making Automotive SoCs Truly Safe Why functional safety changes the verification game? Most SoC verification teams know how to prove a chip meets its functional specification. You write and run simulations, close coverage, debug mismatches, and tape out. But in automotive design — especially when working to ISO 26262 — the job isn’t done when […]

LLM-Aided RTL Design and Verification in Pre-Silicon Flows The integration of large language models (LLMs) into semiconductor pre-silicon workflows has moved from isolated academic prototypes to production-grade deployments in leading EDA environments. In this emerging paradigm, generative models are not limited to assisting with documentation or simple code generation; they actively participate in RTL creation, […]

When AI Acts Like a Threatened Human: Exploring Agentic Misalignment: A Deep Dive for Businesses Artificial Intelligence (AI) is transforming how businesses operate, with AI agents taking on increasingly autonomous roles in areas like finance, legal, and IT. These agents, powered by advanced large language models (LLMs), can handle complex tasks with minimal human oversight. But […]

AMD’s Game-Changer: Instinct MI350/MI400 & Helios—Delivering Open, Scalable AI Infrastructure In our ongoing series on AI accelerators, we previously explored the hardware fueling the AI revolution. Now, we turn our focus to AMD’s latest unveilings—the Instinct MI350/MI400 GPUs and Helios rack-scale system. These innovations tackle critical bottlenecks in AI infrastructure, positioning AMD as a key […]

Deep-Tech Challenges in 2nm Physical Design Stage 1. Physical Implementation Standard Cell Design & Placement GAA introduces discrete nanosheet widths (e.g., 2/3/4 stacks), forcing standard cells to be quantized, which reduces flexibility in sizing and optimization. Cell height (track-based design) is no longer easily scalable due to BEOL and BSPDN constraints – placement becomes non-uniform and harder to optimize. GAA-based […]

AI Accelerators: Powering Embedded Systems, Edge Computing, and On-Device LLMs Introduction AI accelerators—specialized hardware like NPUs, TPUs, GPUs, FPGAs, and ASICs—are revolutionizing how real-time AI operates in smart devices, from augmented reality (AR) glasses to autonomous vehicles. These accelerators are designed to handle compute-heavy tasks such as matrix multiplications and convolutions, enabling powerful AI inferencing […]

Comparing GDS-II Files and Mask Sets in IC Design & Manufacturing GDS-II (Graphic Database System II) and mask sets are two related but distinct concepts in the semiconductor design and manufacturing flow. GDS-II refers to the digital layout files used at the end of the design phase, whereas a mask set refers to the physical […]

AI-Generated Visual Threats: Solutions and Trends The unchecked proliferation of AI-generated visuals—ranging from deepfaked executive videos to convincingly forged invoices and contracts—poses a critical threat to corporate trust and operational integrity. These synthetic assets, which are increasingly easy to produce, cheap to distribute, and difficult to detect, are undermining financial integrity, brand reputation, security workflows, […]

AI in Real-World Chip Design Workflows: A Technical Overview Introduction: Artificial intelligence (AI) is increasingly woven into the semiconductor design flow, helping engineers handle the exploding complexity of modern chips. From high-level architecture decisions to final tapeout, AI techniques (especially machine learning and reinforcement learning) are optimizing tasks that traditionally required extensive human effort. Major […]