Ethernet Fabrics and the Rise of Open AI Networking Abstract Artificial intelligence has transformed datacenter architecture. The challenge today is not just how fast a single GPU can compute, but how efficiently tens of thousands of accelerators can work as one coherent, distributed system. For the past two decades, InfiniBand has dominated this role, offering […]

How Large Language Models Are Quietly Changing RTL Design? RTL design has always been one of the most crucial – and complex – steps in digital chip development. It’s where an engineer takes a specification and expresses it in hardware behaviour using languages like Verilog or System Verilog. As chips become more advanced – especially […]

Verifying AI Chips at RTL: How Foundation Models Are Transforming Design Assurance Modern AI chips are not general-purpose processors. Their RTL design logic is optimized not for instruction throughput, but for dataflow acceleration, parallel computation, and high-efficiency matrix operations. These chips integrate systolic arrays, sparsity-aware data paths, configurable tensor engines, and hierarchical memory systems. This […]

Making Automotive SoCs Truly Safe Why functional safety changes the verification game? Most SoC verification teams know how to prove a chip meets its functional specification. You write and run simulations, close coverage, debug mismatches, and tape out. But in automotive design — especially when working to ISO 26262 — the job isn’t done when […]

LLM-Aided RTL Design and Verification in Pre-Silicon Flows The integration of large language models (LLMs) into semiconductor pre-silicon workflows has moved from isolated academic prototypes to production-grade deployments in leading EDA environments. In this emerging paradigm, generative models are not limited to assisting with documentation or simple code generation; they actively participate in RTL creation, […]