LLM-Aided RTL Design and Verification in Pre-Silicon Flows

The integration of large language models (LLMs) into semiconductor pre-silicon workflows has moved from isolated academic prototypes to production-grade deployments in leading EDA environments. In this emerging paradigm, generative models are not limited to assisting with documentation or simple code generation; they actively participate in RTL creation, iterative repair, verification collateral synthesis, and tool-guided methodology adoption. Unlike earlier automation that relied on rigid templates, LLMs can interpret natural-language specifications, correlate them with design artifacts, and perform multi-step reasoning in closed feedback loops with compilers and simulators.

One example, adapted from NVIDIA Research’s VerilogCoder, illustrates the new design workflow. A team implementing a configurable UART IP began with a protocol specification in English. The LLM parsed the document, extracted the module requirements, and produced synthesizable Verilog for transmitter and receiver paths. When automated simulation revealed a parity bit mismatch in one configuration, the multi-agent system traced the error back to an AST node for the parity generator, proposed a fix, and re-ran the simulation until the test suite passed. This sequence compressed what would have been roughly 12 engineer-hours of initial coding and debug into under 3 hours, with the human role reduced to validation and integration. Benchmarks such as RTLLM 2.0 now explicitly model such closed-loop generation cycles, measuring pass rates, iteration counts, and repair efficiency; controlled experiments report over 90% functional correctness on modular designs.

Verification has seen similar gains, especially in the translation of unstructured specifications into formal properties. At a mixed-signal SoC startup, engineers faced a 65-page PDF describing the analog–digital interface between a temperature sensor and a power management unit. Using an AssertLLM-derived internal tool, the document was segmented into discrete requirements, timing diagrams were cross-referenced, and relevant signal names were extracted from the RTL. The system generated SystemVerilog Assertions for each requirement, such as the rule that if the over-temperature flag persists for more than 5 ms, the PMU must shut down within 50 μs. These assertions were tested in a simulation harness, with model-driven corrections applied until all compiled and passed. The final SVA set was automatically inserted into the project’s UVM scoreboard and monitor components, complete with associated coverage points. This automation reduced manual assertion coding effort by roughly 70% and caught two subtle handshake bugs before tape-out, without bypassing mandatory human sign-off.

Commercial EDA ecosystems are rapidly consolidating these capabilities. Synopsys.ai Copilot integrates LLM-driven conversational guidance and generative features into its design, verification, and sign-off tools, while Cadence.AI and ChipGPT enable natural-language design interrogation, and Cerebrus applies reinforcement learning to PPA exploration. Siemens, in collaboration with Microsoft, is adapting industrial copilots to pre-silicon engineering workflows. Across these offerings, deployment models emphasize on-premises or secure VPC execution and contractual safeguards against training on customer data.

Nevertheless, challenges remain. Specification ambiguity can lead to functional errors that slip past basic regression tests. Scaling from single-IP blocks to complex SoCs with multiple power and clock domains presents substantial reasoning and verification hurdles. Stochastic LLM outputs also complicate reproducibility, requiring strict output gating and determinism controls in production flows.

The direction of travel points to hybrid engineering loops where autonomous generative agents handle well-defined subproblems, retrieval-augmented copilots accelerate methodology learning, and engineers oversee architecture, design intent, and safety-critical decisions. In this model, measurable productivity gains coexist with the irreplaceable value of human engineering judgment.